Mentor buys into driver information, ADAS and infotainment software
Mentor Graphics has expanded its portfolio of tools and software for the automotive market with its second acquisition of the year in this sector.
Author Archives: Chris Edwards
Focusing coverage for system-level integration
Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.
Qualcomm takes 28nm to China in SMIC deal
Chinese foundry Semiconductor Manufacturing International Corporation (SMIC) is to get a helping hand to develop a production-class 28nm process from Qualcomm Technologies.
IEA takes aim at network-device energy consumption
The International Energy Agency (IEA) has turned its attention to slashing the electricity demands of network-attached devices with a report that says manufacturers and service providers need to look at changes to protocols and features such as energy harvesting.
DVCon India heads to Bangalore
As well as starting up a version for the European market, the Accellera Systems Initiative is taking DVCon to India in the early autumn.
OpenPDK accelerates design kit production at ST
STMicroelectronics is using the OpenPDK standard from Si2 to speed up the production and delivery of process design kits (PDKs) and asks for wider adoption by foundries.
Sensor-hub infrastructure moves to open source
With the aim of accelerating the development of applications and algorithms that harness sensor fusion, startup Sensor Platforms has released as open source its Open Sensor Platform (OSP).
Accellera releases version 1.2 of UVM
Accellera has released the latest version of the Universal Verification Methodology (UVM) class reference document, with additions to the way in which testbenches can handle messages and registers.
14nm FD-SOI pushes strain and body bias for power savings
At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
Verilog-AMS release adds to power-aware analog modeling
Accellera has published version 2.4 of the Verilog-AMS standard for mixed-signal modeling and verification as the group works on a merger of the language with SystemVerilog.