DFM

August 13, 2018
Dina Medhat is a Technical Lead for Calibre Design Solutions at Mentor, a Siemens Business. She has held a variety of product and technical marketing roles at the company, and received her BS and MS degrees from Ain Shames University in Cairo, Egypt. She is currently a PhD student at Ain Shames University.

Managing waivers in reliability verification

Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
Expert Insight  |  Tags: , , , , , ,   |  Organizations:
May 31, 2018
layout file feature

Layout-database file control: the missing link

The authors descirbe a new signature-based approach to resolving the content of layouts in GDSII, OASIS and other formats.
Article  |  Tags: , , , , , ,   |  Organizations:
April 23, 2018
data validation featured image

The three critical data validation points in a design flow

Why design data integrity matters from cell design to tapeout. These techniques will help ensure your validation process is as comprehensive as possible.
Article  |  Tags: , , , , , , , ,   |  Organizations:
April 17, 2018
Guido Groeseneken is an Imec fellow, researching advanced devices and the reliability physics of sub-10nm CMOS technologies.

Reliability research helps to create new technologies

Insights from research into reliability at Imec led to self-learning chips, security technologies, and finFET biosensors.
Expert Insight  |  Tags: , , , , ,   |  Organizations:
March 29, 2018
Two wafers fabbed at Imec

3DIC technology provides performance boosts

3D integration technology has split into a number of different approaches, each of which brings a different combination of benefits in terms of performance.
Article  |  Tags: , ,   |  Organizations:
February 1, 2018
Design space exploration feature

Design space exploration finds hotspots during early process development

A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
January 15, 2018
Physical Verification Efficiencies - featured image

Three ways to lift productivity during physical verification

How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
Article  |  Tags: , , , ,   |  Organizations:
November 24, 2017
John Ferguson is the Director of Marketing for Calibre DRC Applications at Mentor, a Siemens Business, in Wilsonville, Oregon, with extensive experience in physical design verification. He holds a BS degree in Physics from McGill University, an MS in Applied Physics from the University of Massachusetts, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

Assessing the true cost of node transitions

John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
October 27, 2017
Featured image - double patterning at advanced nodes

Catch multi-patterning errors clearly at advanced nodes

How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Article  |  Tags: , , , , , ,   |  Organizations:
September 21, 2017

Yield is money – and other truths of diagnosis-driven yield analysis

Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors