Tech Design Forum Briefing


Briefing Authors

Paul Dempsey

Paul Dempsey Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.

Luke Collins

Luke Collins Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.

Chris Edwards

Chris Edwards Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
May 29, 2019

Synopsys introduces fast full-chip yield analysis and optimization tool

Synopsys has released PrimeYield, a tool for analysing and optimizing the yield of a design before it is made.

May 28, 2019

Cadence expands Protium for rack-based prototyping

Cadence has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.

May 28, 2019

DAC 2019 preview: OneSpin Solutions

OneSpin is bringing recent product launches to DAC and will have technical experts presenting within the conference’s Designer Track.

May 28, 2019

ESDesign West gets HoT

Heart of Technology (HoT) founder and Jim Hogan talks about the event at the upcoming ESDesign West show in San Francisco.

May 28, 2019

ARM adds Cortex-A77 and Mali-G77 cores for 5G and ML

The company is also bundling its new CPU and GPU cores in a premium IP platform that can be tuned for next generation applications and devices.

May 27, 2019

Automotive complexity drives DFT to the RTL

Design-for-test can no longer be left until the gate level for increasingly sensitive designs aimed at newer processes.

May 24, 2019

OneSpin extends line-up for AI FPGA and RISC-V verification

The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.

May 24, 2019

DAC 2019 Preview: Breker Verification Systems

The company will highlight features within its Trek suite that comply with but then go beyond the capabilities of the Portable Stimulus Standard.

May 23, 2019

AI and ML fuel Catapult and Calibre updates

Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.

May 21, 2019

Achronix deploys network on chip for faster FPGAs

Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.

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