Synopsys has released PrimeYield, a tool for analysing and optimizing the yield of a design before it is made.
Cadence has developed a version of its Protium prototyping engine that supports larger designs and which is intended to go into data-center racks.
OneSpin is bringing recent product launches to DAC and will have technical experts presenting within the conference’s Designer Track.
Heart of Technology (HoT) founder and Jim Hogan talks about the event at the upcoming ESDesign West show in San Francisco.
The company is also bundling its new CPU and GPU cores in a premium IP platform that can be tuned for next generation applications and devices.
Design-for-test can no longer be left until the gate level for increasingly sensitive designs aimed at newer processes.
The formal specialist is extending its line for Intel FPGAs that target areas such as AI/ML and HPC, and building out a RISC-V suite focused on ISA compliance.
The company will highlight features within its Trek suite that comply with but then go beyond the capabilities of the Portable Stimulus Standard.
Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.
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