The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.
A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.
At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.
The 69th annual IEEE IEDM has issued a call for papers seeking the world’s best original work in all areas of microelectronics research and development.
Single-device tracking in the chiplet and multi-chip age needs a boost to deliver accuracy and greater production efficiency.
Siemens is integrating the Supplyframe platform with the Xpedition PCB-design software to give engineers better visibility into component availability.
AT&S and Imec partnered to develop a way of putting low-loss waveguides into conventional PCBs to support D-band automotive radar and 6G modules.
Siemens has published a white paper that examines whether package designers need to adopt IC tools and design styles in the move from organic packages to 2.5DIC packages.
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