As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
AMD worked with Microsoft and Azure to cut DRC runtimes and control memory usage for a 7nm cloud-based design.
Moortec has reworked its thermal-sensing core design to allow for finer-grained use on SoCs being designed for the 5nm node.
Real Intent has launched a DFT tool intended to relax the bottlenecks that occur as an SoC project moves into its final phase ahead of tapeout.
A technical paper originally presented at DVCon USA 2020 simplifies the creation of coverage strategies using manual, automated and verification IP components.
The IEEE plans to stage the 66th International Electron Device Meeting as a physical event in mid-December.
DVCon US is to repeat sessions online from today until the middle of August, with exclusive access to registered attendees through early June.
Adaptive power-aware clocking and buried rails are among the techniques to be explored at the 2020 VLSI Symposia.
A white paper details the parasitic extraction technology needed to help design high-performance RF SoCs.
Live and on-demand videos as well as You Tube ‘tips and techniques’ clips form part of a wide ‘work at home’ support package from Mentor.
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