Refining DTCO to bridge data walls in system design
DTCO (design technology co-optimization) looks to address systemic verification challenges but the process still needs to be extended.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Early package assembly verification for faster, better results
Make it easier to capture issues in 2.5D and 3D designs with multiple chiplets and emerging challenges with this ‘shift left’ approach.
Arm embraces Transformers with faster NPU
Arm has launched what the company claims is its highest-performance and most-efficient AI accelerator.
Get a comprehensive overview of ‘Shift Left’ for physical verification
How the various features within today’s Calibre physical verification family help designers shift left tasks and cut time-to-market.
Arteris extends safety and speed for NoC
Certification to ISO 26262 for automotive systems and compatibility with the latest Arm9 generation of processors and the CHI-E interface are among the updates to Arteris’ Ncore cache-coherent on-chip network IP framework.
Two projects to deliver digital twins for software-defined vehicles
Arm is working with Cadence and Siemens on separate projects to support its plans in the SDV space.
DVCon Europe calls for papers for 2024 event
DVCon Europe is looking for papers to be presented at this year’s event in mid-October.
Latest version of Verilog-AMS ready for release
The board of directors of Accellera Systems Initiative has approved the 2023 edition of the Verilog-AMS standard for release.
Cadence to work on IP for Intel 18A
Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.
Accellera forms working group for mixed-signal interfaces
Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.