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Accellera Systems Initiative has begun a project that may result in the creation of a standard to address security assurance for semiconductor IP cores.

DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.

The Accellera Portable Stimulus Working Group has released for public review its current proposal for the verification standard it is working on.

Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.

June's DAC will see the culmination of a contest involving more than 100 teams vying to demonstrate the best use of machine learning on embedded hardware in a flying drone.

With the aim of making it easier for embedded devices to cooperate in an IoT environment, Mentor has launched a cloud connectivity and management framework.

Ceva has decided to include neural network, vector processing and customized instruction sets in an IP platform for 5G NR terminals.

Arm plans to use its cryptography cores and technology from its Simulity Labs acquisition to SIM-based security into IoT devices.

Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.