EDA

A flexible and still evolving range of 5G standards requires methodologies that can handle massive test.

DVCon US 2020 is to end a day early as a result of the COVID-19 coronavirus outbreak and released an updated agenda.

A new technical article discusses Renesas' addition of SLEC to its SystemC and RTL flows and the improvements it achieved in time and coverage..

Portable stimulus pioneer Breker will feature across the DVCon program also highlighting its work with RISC-V.

The Electronic System Design Alliance will discuss the benefits it offers for design and verification, and has added Avery Design Systems.

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.

Accellera has set up a working group with the aim of developing interoperability standards for functional safety.

By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.

The parser specialist has built a loyal fanbase across the electronics system design infrastructure with users now lining up to mark its 20th birthday.