Synopsys speeds ATPG, adds ISO 26262 certification

By Luke Collins |  1 Comment  |  Posted: July 12, 2016
Topics/Categories: Product, Tested Component to System  |  Tags: , , , , ,  | Organizations: , , ,

Synopsys has introduced TetraMAX II, an ATPG and diagnostics solution, which it says runs ten times faster and uses 25 per cent fewer patterns than the previous offering, cutting the time and resources involved in IC test or enabling users to improve tests without increasing costs.

The tool has already been certified by an independent assessor for use in achieving the ISO 26262 automotive functional safety standard.

TetraMAX II has been developed in response to general industry trends including the growing use of finFETs, increased complexity with designs of 5 million placed instances becoming commonplace, the emergence of more subtle defects, and demands for greater quality (i.e. fewer than 1 defect per million parts) from the automotive industry.

These trends have been felt in the test arena as an increase in patterns with each new process node, longer ATPG runtimes, and so greater delays before silicon can be tested after first silicon is delivered. And although the servers on which test tools run have steadily gained processor cores over the past few years, the parallelisation of ATPG algorithms has become limited by their memory usage.

The tool uses test generation, fault simulation and diagnosis engines, first discussed at the International Test Conference in October 2015, tuned for speed, memory efficiency, pattern generation and fine-grained multithreading of the ATPG and diagnosis processes. The algorithms are claimed to reduce average memory use threefold, as well as offering the tenfold speedup and 25 per cent reduction in the number of patterns already mentioned. This enables all the available server cores to be used, rather than having to stand idle because of memory constraints.

The reduction in the number of test patterns derives from a different approach to test pattern generation, which moves away from a sequential approach to a much more parallelizable strategy in which a pattern is created for each fault and then those patterns are superposed to create more powerful combined patterns that are each optimised to detect the maximum number of faults.

TetraMax II re-uses the production-proven design-modeling and rule-checking infrastructure of the previous tool, as well as its user and tool interfaces, so that it can be deployed quickly. TetraMAX II links to Synopsys Galaxy Design Platform tools, such as DFTMAX compression, PrimeTime timing analysis and the StarRC extraction tool, and related tools for yield management and debug.

Certification to the ISO 26262 automotive functional safety standard has been provided by SGS-TÜV Saar, an independent accredited assessor. It should give designers confidence that they can use TetraMAX II for safety-critical automotive applications, and speed up the process of achieving functional safety qualification for automotive ICs, up to the most stringent requirements for automotive safety integrity level ASIL D.

This will be important in the development of advanced driver assistance systems, a step on the way to truly autonomous vehicles. TetraMAX II enables engineers to target higher levels of IC test quality, by testing for multiple fault models without increasing test costs or time too much.

Gudrun Neumann, product manager of functional safety software at SGS-TÜV Saar, said: “SGS-TÜV Saar’s certificate for TetraMAX II is based on a successful functional safety evaluation of validation processes against the requirements of ISO 26262.”

Separately, both STMicroelectronics and Toshiba have committed to using TetraMAX II. STMicroelectronics did an evaluation of the tool on a multi-million-gate FD-SOI SoC design and found that it was ten times faster than the previous approach, without affecting the previous approach.

Roberto Mattiuzzo, SoC integration and DFT methodologies manager in STMicroelectronics’ digital and mixed processes ASIC division, said: “With these results, we are confidently testing first-silicon samples earlier and reducing tester time, too.” 

Toshiba’s evaluation demonstrated up to a 50% reduction in pattern count, significantly faster runtime and advanced power-aware features, and so the company plans to use it consumer SoCs.

“Long ATPG runtimes and increasing test pattern counts are becoming bigger challenges on our large-scale SoC designs,” said Kazunari Horikawa, senior manager at Toshiba’s design technology development department. “We confirmed through an evaluation that TetraMAX II shortens ATPG execution time and reduces the number of test patterns by up to 50% while maintaining the quality of test.”


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