Cadence packages VIP for ten protocols
Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
EDA
UltraSoC to support RISC-V
UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
Event: How ISO 26262 is driving automotive DFT requirements
Webinar explores the impact of ISO 26262 on DFT requirements, and what is being learnt from the introduction of the standard at ON Semiconductor.
Synopsys adds ultra-low power security processor IP
Ultra-low power security processor IP includes defences against side-channel attacks, data and instruction encryption, DSP options for sensor processing and more.
Design trade-offs in using DDR4 memory for enterprise applications
A look at some of trade-offs involved in building large system memories for enterprise equipment using DDR4 IP.
Creating a reference design flow for 10nm processes: video
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
Cadence building photonics environment around Virtuoso
Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
Chinese dates set for Asia-Pacific editions of Mentor Forum
Wally Rhines headlines as keynote at free technical events set for Shanghai on August 30 and Beijing on September 1.
Cadence adds floating point to Fusion
Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
Synopsys speeds ATPG, adds ISO 26262 certification
Synopsys has introduced TetraMAX II, a faster and more parallelisable ATPG and diagnostics solution, which is now also certified for use in ISO 26262 compliant automotive designs.