EDA

What does it take to build data converter IP that will meet the reliability and functional safety requirements of the automotive industry?

The Electronic System Design Alliance will discuss its recent decision to join SEMI and highlight DAC's new Infrastructure Alley.

Early users of the new P&R integrated physical verification tool say time-to-sign-off was cut by 40% and above.

Power analysis specialist will showcase the 2.0 edition of its PowerBaum analysis and modeling suite at DAC.

DAC 2018 will see Synopsys focusing on close links with foundry partners, as well as exploring ways to exploit the potential of machine learning, in both SoC architectures and SoC design flows.

The parser specialist will demonstrate its recently announced INVIO integration to speed development around VHDL and SystemVerilog.

Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design

Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.

Synopsys has extended its range of semiconductor IP for use in advanced driver assistance (ADAS) and autonomous vehicle SoCs with the launch of embedded vision processor blocks that have been given safety enhancements.