Mojy Chian, senior vice president of GlobalFoundries, told this year’s Design Automation and Test in Europe conference in Dresden that although DRC has been based on checking layout proximity and shapes to date, “we believe that pattern-based physical verification is the future for DRC.”
Mentor Graphics’ consulting division worked with GlobalFoundries to extend the Calibre tool suite to support pattern recognition.
“We have put in place a pattern recognition and correction technology,” said Chian. “DRC+, as we call it, searches the layout for yield-limiting patterns, and then corrects them.”
The company claims that using the technique resulted in a “significant” yield improvement on a test chip. The DRC+ flow is available for customers of GlobalFoundries’ 45/40 and 32/28 nm processes.
The flow filters the design database to identify areas that require DFM improvement, applies the necessary enhancements, and then rechecks the modified layout to ensure that the changes do not introduce DRC violations. The flow uses the Calibre nmDRC, Calibre YieldAnalyzer, and Calibre YieldEnhancer tools to automatically perform metal widening, via doubling, and via enclosure improvements, including support for rectangular vias.
Results were validated by comparing the test silicon with the Mentor test and yield analysis tools, including Tessent TestKompress, Tessent Diagnosis and Tessent YieldInsight. Test failures were traced back to layout locations and the root cause was determined using physical failure analysis to correlate the failures to specific design-based limiters that could be eliminated using DFM enhancements.
Luigi Capodieci, director of DFM/CAD and R&D Fellow at GlobalFoundries, said. “We like that the flow is highly modular and scalable, which allows us to easily move it to new processes and to extend it to address additional DFM issues as we uncover new design-based yield limiters.”