DVCon US 2020 preview: SmartDV
The latest in MIPI and DDR design and verification IP as well as protocol debug are highlights in SmartDV’s DVCon program.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Embedded World 2020 preview: Mentor
Six papers, a dedicated automotive sessions and demos including the use of the Nucleus for RISC-V are among highlights in Mentor’s Embedded World agenda.
Accellera moves to working-group stage for functional-safety standard
Accellera has set up a working group with the aim of developing interoperability standards for functional safety.
Debug connects with manufacturing test to cut product recall costs
UltraSoC has kicked off a collaboration with PDF Solutions to build a system better able to use runtime information to identify devices that are likely to fail in the field and so reduce the impact of product recalls.
AI processor company opts for Analog FASTSPICE and Symphony
Mythic will use the Mentor tools for its analog-targeted intelligence processing units.
Arm adds AI to Cortex-M cores
Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.
Toward more efficient formal strategies for deadlock
Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn’t it be better if you could automate that work? Now you can.
Earlier latch-up prevention with topology-based analysis
By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
SureCore provides 30-day test for SRAM compiler
SureCore has started running 30-day trials of its low-power memory compiler.
Verific celebrates two decades of parser pre-eminence
The parser specialist has built a loyal fanbase across the electronics system design infrastructure with users now lining up to mark its 20th birthday.