TSMC fills in sub-nodes as EUV gains ground
TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process.
Tech Design Forum Briefing
Briefing Authors
Paul Dempsey
Paul Dempsey has been a technology journalist for 20 years. His work has also appeared in EETimes, Red Herring and specialist journals published by the Financial Times.
Luke Collins
Luke Collins is a freelance technology journalist with 22 years’ experience. He is a former Editor-in-Chief of Electronics Times in the UK, and co-founded the IP9x series of conferences.
Chris Edwards
Chris Edwards has spent two decades covering electronics and EDA. He is a former Editor-in-Chief of Electronic Engineering Times UK and electronics editor of the IET's Engineering & Technology.
Cadence uses machine learning to trim constrained-random runtimes
Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
How to handle PCB constraints for IoT designs
An RF Laboratories engineer provides some tips and techniques in the context of the PADS Professional suite.
Open-RAN puts more focus on emulation in testing programs
Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.
Second formal check aids deadlock hunting
Arm works with EDA to find new efficiencies based on extra CTL-based check in Questa runs.
Litho hotspot analysis gets machine-learning turbocharge
A Mentor-Samsung collaboration cuts the need for model-based analysis and speeds analysis runtime by as much as 20X.
Open and proprietary verification tools home in on RISC-V core quality
DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
Accellera IP security group expects standard by year end
The chair of Accellera’s IP security assurance working group expects the draft standard for hardening hardware core to be out by the end of the year.
DAC Pavilion focuses on cloud-scaling issues
Talks in the Design-on-Cloud Pavilion at this year’s DAC demonstrated how the question over its usage is not so much whether design could or should migrate to the cloud but how to optimize cost and performance when it’s there.
3D integration technologies will blend says TSMC chief scientist
DTCO and 3D integration will dominate scaling in the coming decade, TSMC chief scientist Philip Wong claimed in his keynote at DAC on Monday