Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.
Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.
Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.
How to enhance an 'ideal' parastitic extraction strategy to create a full 3D assembly-level parasitic netlist for simulation and circuit analysis.
Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?
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