hardware-software coverification

Part three of our series looks at the choices you face as you decide whether to build or buy a board.

Part two of our series on FPGA-based prototyping looks at two critical factors to address before a project begins: budgeting and high-level implementation.

This multi-part series addresses various aspects of FPGA-based prototyping. Future installments will address budgeting and implementation, but we start by looking at why the technique is generating so much interest.

This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.

We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.

While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging

The growing verification challenge, and how to address it by coordinating multiple debug strategies.

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.

The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.

Building a prototype SoC in one or a set of FPGAs can aid field trials, software development and hardware/software integration. But it's not easy, so the decision to go ahead needs careful consideration.