Mentor Graphics

December 29, 2015
Stephen Pateras

Memory BIST for automotive designs

Behind the drivers for memory BIST innovation in areas such as power-on self-test, destructive and non-destructive techniques, and faster memory repair.
Expert Insight  |  Topics: EDA - DFT  |  Tags: , , , , ,   |  Organizations:
December 9, 2015
Emulation IoT Networking Challenges

Emulation overcomes the five main IoT and networking verification challenges

More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.
November 2, 2015

How to cut verification time with VIP

This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations: ,
September 18, 2015
Featured image: PHY VIP Sep 15

How PHY verification kits overcome traditional VIP limitations

Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , , , , , , ,   |  Organizations:
August 24, 2015

A scalable RTOS and other essentials for embedded wearables development

The wearables market is booming. Successful development depends on assembling the right software and hardware tools. Here's a primer on what to look for.
June 30, 2015
Mark Handover is an applications engineer with Mentor Graphics

Back to basics – doing formal the right way

Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
Expert Insight  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:
May 29, 2015
Mentor Graphics/Wilson Research Group Functional Verification Study

Smaller designs face greater risk of respins

Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
May 28, 2015
Featured image PCB Design for the mid-market

PCB tool innovation from the middle out

Mid-market users are driving richer features and cost competition into PCB design software like never before, largely thanks to the Internet of Things.
May 22, 2015
Eight steps for efficient PCB manufacturing and assembly - Part Two

Eight steps for efficient PCB manufacturing and assembly – Part Two

Second in a two-part series, describing critical rules that should underpin PCB manufacturing, and how new technologies overcome increasing complexity.
May 18, 2015
SMT p&p machine featured image - 8 rules for PCB manufacturing

Eight steps for efficient PCB manufacturing and assembly – Part One

First in a two-part series, describing critical rules that should underpin PCB manufacturing, and how new technologies overcome increasing complexity.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors