Behind the drivers for memory BIST innovation in areas such as power-on self-test, destructive and non-destructive techniques, and faster memory repair.
More protocols, multibillion-gate designs, minimized power, burgeoning software and, for networking, hundreds of switch and router ports emphasize the need for scalable, virtualized emulation.
This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
The wearables market is booming. Successful development depends on assembling the right software and hardware tools. Here's a primer on what to look for.
Considering design style, assertions, engines and coverage can help ease the development of an effective formal verification test plan
Research study suggests the maturity of your verification flow determines the likelihood of first-pass success far more than the complexity inherent in design size.
Mid-market users are driving richer features and cost competition into PCB design software like never before, largely thanks to the Internet of Things.
Second in a two-part series, describing critical rules that should underpin PCB manufacturing, and how new technologies overcome increasing complexity.
First in a two-part series, describing critical rules that should underpin PCB manufacturing, and how new technologies overcome increasing complexity.
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