In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
In part two of this series, Ashish Darbari introduces a checklist to address verification challenges and build the meta model.
Accellera's Portable Stimulus standard aims to improve verification efficiency and the reuse of test IP across the entire design life cycle.
Emulators have come a long way since their first introduction nearly three decades ago.
2016 marks the 20th anniversary of the term Electronic System Level (ESL), introduced by Gary Smith in 1996. Where are we now? And how will developments this year push the frontiers of practical ESL design?
In-circuit emulation is attractive but brings with it debug-visibility issues. There are ways to restructure the environment to make bug hunting much more deterministic.
Emulation performance is a key metric in verification. But it is far from being the only consideration. How long it takes to get a design onto a verification platform and aspects such as debug are as important. These factors will control how verification platforms are deployed during a project's life cycle.
Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
The next boost to verification productivity will come from the integration of multiple strategies and tools.
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