June 1, 2012
There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
May 22, 2012
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
May 22, 2012
Correlating production test failure diagnosis with DFM analysis can help identify and understand systematic yield issues, and to find out whether they are linked to DFM violations.
April 25, 2012
Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.
March 21, 2012
Open-source toolchains give companies ultimate control over their development environments, but how many can really afford the resources to debug and develop their own tools? Would they be better off with a commercially supported open-source approach?
August 23, 2011
Mentor’s Dennis Brophy, Cadence’s Stan Krolikoski and Synopsys’ Yatin Trivedi describe how you can prepare to adopt Accellera’s Universal Verification Methodology.
August 23, 2011
The description of the stimulus to a device-under-test is becoming ever more complex. Complex constraint relationships need to be defined, and the use of randomly generated stimulus to achieve comprehensive coverage metrics is proving less predictable and more labor-intensive. Using the combination of a graph-based stimulus description with a more intelligent algebraic constraint solver, a [...]
June 1, 2010
We talked to Mentor Graphics CEO Wally Rhines about the solutions that already exist to combat increasing design complexity.
May 1, 2010
The article offers a case study of the DFM planning and methodology applied during a shrink of Cambridge Silicon Radio's UF6000 system-on-chip from the 130nm to 65nm.
November 1, 2008
New tools and standards encourage communication between the electrical and mechanical domains, says Pawel Chadzynski. Most major electronics companies have separate electrical (ECAD) and mechanical (MCAD) design organizations. Efficient collaboration between these teams throughout the PCB design process can significantly reduce cycle times, lower the risk of re-spins, and improve quality. The first challenge to […]