If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.
Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
PGA has been IC-centric for mainstream 2D configurations. It must become system-centric for 2.5D and 3D systems.
New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
How the company migrated to an OVM-based methodology to design and verify a 30 million-gate ASIC design, on the path to UVM.
Electrical rule checks (ERC) are now available to deal with increasing PCB design complexity, speed project delivery and protect the intellectual property within them.
SoC integration can be accelerated by using virtualization to make the benefits of emulation more accessible to both hardware and software engineers.
Mind how you go. The only truly free thing about open source tools is the download itself. There is, however, a 'third way', matching professional support to these often useful options.
You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
This case study shows how the evaluation of various design options requires a thorough approach to system-level modeling.
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