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CEA-Leti has launched a design center called Silicon Impulse with the intention of lowering the entry barrier to using the FD-SOI process.

The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.

As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond.

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.

'Bling' for fashionistas and the B Ark lot. Apple Watch limps as the S1 SIP fails to offer convincing battery life. Silicon shortfall still dogs wearables.

The Embedded Microprocessor Benchmark Consortium (EEMBC) has released a benchmark suite aimed at applications processors and higher-performance microcontrollers with floating-point units.

Unsettled by attacks on embedded devices such as the point-of-sale terminals used by retailers such as Target and the potential for hackers to target critical infrastructure, the industry focused squarely on security at this year’s Embedded World in Nürnberg, Germany.

Ascent Lint adds checks for DO-254, tighter integration with HDL Coder, more SystemVerilog support and new VHDL and Verilog rules in March update.

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.

A variety of organizations used Embedded World to introduce kits to attract a broader base of developers looking at Internet of Things (IoT) applications.