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Senior verification expert at Imagination Technologies debunks ten myths surrounding the use of formal techniques in SoC design and verification

This year's Heart of Technology philanthropic event on Monday June 8 promises craft beers, music, a pool tournament and more, all supporting a great cause.

Mentor Graphics has released a programming interface to its Veloce emulators intended to support faster and more accurate power estimation.

Intersil is aiming to remove the intermediate converters from the power buses of industrial systems using a buck converter that can take a voltage of 48V and provide power rails down to 1V.

TCAD specialist GSS says nanowire transistors look practical down to 5nm but that designers need to carefully explore how the wires are shaped as quantum-confinement effects take hold

Cadence has launched the 16.6 release of its Allegro PCB-design portfolio, adding modules for manufacturing documentation and design-rule preparation aids.

Formal-verification specialist OneSpin is setting up its own equivalent of an app store, building on top of a formal engine the company now licenses to other companies.

Agnisys is adding automated verification of SoC register maps to its IDesignSpec tool for defining and specifying registers and their behaviours, deploying both a dynamic and a formal version.

Imagination Technologies plans to introduce support for virtualization across all its processor cores, including signal processors such as the Ensigma family, as part of a plan to improve SoC security.

ARM and Unicef have teamed up to try to find new sources of designs for the developing world, and to stimulate innovation there.