EDA Topics

EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.

Moving to a finFET process means considering process readiness, cost and yield, as well as the traditional power, performance and area advantages

This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.

Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.

FinFET and 3DIC technologies bring with them not just higher performance but an increased need for accurate parasitic analysis.

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.

The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.

We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.

The ISO 26262 safety standard lays out a number of best practices for the automotive industry and for suppliers. Formal verification provides a way of streamlining the verification of SoCs that need to conform to the standard.

The argument for an integrated approach to SoC verification