Six key criteria for deciding to migrate to a finFET process

By Prasad Saggurti |  No Comments  |  Posted: August 27, 2014
Topics/Categories: EDA - IC Implementation, IP - Selection  |  Tags: , ,  | Organizations: , , , , ,

Prasad Saggurti is the product marketing manager for embedded memory IP at Synopsys.Prasad Saggurti is the product marketing manager for embedded memory IP at Synopsys.

Should your next SoC be built on a finFET process, or should it stick with 28nm or 20nm planar options? It’s a question facing leading SoC developers as the foundry industry wrestles with the costs and complexity of this latest process transition.

Things used to be simpler. Foundries would develop a denser process and designers who used it would ‘automatically’ gain improvements in the power consumption, performance and area of their designs – the so-called PPA benefits. Things aren’t that simple for the shift to finFETs, so how do you decide whether to make the move?

Before we answer that, let’s recap what a finFET is and why it matters.

Why finFETs matter

FinFETs are a response to the increasing power consumption of planar transistors, caused by leakage through the bulk silicon under the channel at advanced geometries. By moving the channel into a three-dimensional ‘fin’ above the surface of the bulk, the gate can take much stronger control of the channel, and leakage through the bulk is reduced. Lower dopant levels in the channel reduce variability, enabling lower threshold voltages and hence lower operating voltages, which ultimately reduces power consumption.

There are downsides to the finFET. Because you can’t vary the shape of the fin, the effective width of the transistor is quantized, which creates a new constraint for analog designers. Because And since the channel is isolated in the fin, you can’t do body biasing to reduce leakage, or boost performance at the cost of extra leakage. Parasitics are higher, because of the dimensions of the device and its 3D shape. There are also new aging and self-heating mechanisms to be taken into account in circuit design.

PPARCY – a framework for choosing a new process

FinFETs enable us to keep shrinking transistors without losing their performance advantages in a flood of leakage current. So why not make a PPA comparison between your current planar process and an emerging finFET process and make your decision on that basis?

We’re finding the decision-making process is not quite that simple. We believe that you need to make your choice using six criteria – power, performance, area, process readiness, cost, and yield – what we’re calling the PPARCY framework. Let’s take them one by one.


FinFET processes have about half the leakage of the preceding planar processes, according to what we have seen in silicon from multiple foundries. Dynamic power has come down, and lower leakage enables lower threshold and operating voltages.


We think you’ll see an average 30% speed increase going from a 28nm planar to a 16nm or 14nm finFET process.Using our ARC processor cores as a measure, when we compare our 12.5-track library at 28nm to our 16nm 9-track library, the 9-track finFET library offers greater performance. That’s making people ask whether they’ll even need a library with more tracks at 16nm.


New process nodes usually bring a 50% area shrink, although the amount of improvement has been declining recently because of routing issues in such dense processes. We’re finding that for cells such as SRAMs, you can get about a 40% area reduction moving to a finFET process.


There’s not much point in worrying about moving to finFETs if the processes aren’t ready.

This is what has been publicly announced:

  • Intel has 22nm and 14nm FfinFET processes, and has customers taping out on both
  • TSMC expects customers to be in production with its 16nm FfinFET process later this year. It says the process will be 40% faster than a 20nm planar process, for the same power
  • Samsung has already built products in its 14 LPE process, with an LPP variant to follow
  • GLOBALFOUNDRIES is ready to offer its version of Samsung’s 14LPE and 14LPP process, using a common GDS file
  • UMC has been working with Synopsys on design enablement for a finFET process

Synopsys has been building logic libraries and memory compilers along with interface IP such as PHYs and SERDES blocks for many of these processes.


We expect manufacturing costs to be much higher than planar processes due to the tighter dimensions, which demand double-patterning lithography, and additional manufacturing complexity. So it is unlikely that area reduction, even if you can achieve the full 50%, will offset the extra cost.


FinFET processes are stabilizing much faster than previous nodes have. But moving to finFETs has introduced new failure mechanisms, so the BIST algorithms you used for 28nm designs won’t catch all the failures in a finFET process.

We’ve authored new finFET-specific BIST algorithms for our test offerings, and added row redundancy to the usual column redundancy in our memory IP to deal with multiple word-line failures.

Making sense of PPARCY

So should you move to a finFET process for your next SoC, or not?

The answer is that area improvements alone won’t make moving to finFET processes worthwhile. FinFET designs will have to take the area gains and extract extra value from the ability of the process to enable end products whose performance and/or battery life are so much better than the planar equivalents that customers will pay a premium.

Who are the early finFET adopters? On the performance side, they are likely to include server CPU and discrete GPU designers, high-performance networking vendors and even Bitcoin miners. Meanwhile it’s the smartphone and tablet vendors who will value the combination of performance and battery life that finFET processes bring to the consumer market.

So should you move? We say the processes are ready, the tools and the IP are ready, and so, if you need the improved performance, the lower power, and the greater integration – and have customers who will pay a premium for products that rely on a combination of those factors – then you should make the move sooner rather than later.

If you’re still not sure, check out the six criteria we list above – when it comes down to it, only you can know how to solve the PPARCY equation for your next product.

Further information

For a more detailed discussion of this topic, please watch the webinar.


Prasad Saggurti is the product marketing manager for embedded memory IP at Synopsys. Prior to Synopsys, Prasad held senior engineering and marketing roles at MoSys, ARM, National Semiconductor and Sun Microsystems. Prasad has an MSEE from the University of Wisconsin-Madison and an MBA from the University of California-Berkeley.

Company info

Synopsys Corporate Headquarters
700 East Middlefield Road
Mountain View, CA 94043
(650) 584-5000
(800) 541-7737

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