The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.
The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
Parasitic extraction reveals the impact of implementation on the theoretical performance of IC designs.
The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
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