EDA Topics

The 14nm and 16nm processes cover a range of technologies and are designed to succeed the 20nm generation. They bring with them a number of design challenges.

Verification coverage attempts to at least provide a partial answer to the question: "How do you know you are finished verifying?" It involves the combination of a number of techniques.

Wreal modeling brings fast methods for simulating mixed-signal designs into the digital environment. And tools have arrived that make it easier to incorporate existing analog IP.

While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging

The encryption chain for today's highly collaborative designs needs to be managed with care.

Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.

Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.

Performing clock-domain crossing (CDC) checks on a flat database is difficult on complex SoCs. Hierarchy improves speed but calls for a smarter approach.

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.

Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.