EDA Topics

'Design for yield' is a familiar term, but the challenges in today's increasingly large projects make a refresher on what it offers particularly timely.

By taking the circuit supply voltage close to that of the threshold voltage or even below, it is possible to optimize low-power VLSI design. But there are pitfalls.

A static-analysis tool that checks for errors in HDL code, lint is becoming an increasingly important addition to simulation for RTL and SoC signoff.

As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.

Design for security is an emerging topic in hardware engineering demanding a more holistic approach that traditional cryptographic implementation.

In the absence of EUV lithography, the primary option for manufacturing on a 10nm process is to extend double patterning. But the options each have issues.

IC designers are becoming increasingly worried about the possibility of third parties inserting malicious 'trojan' circuitry into their ICs.

ProtoCompiler understands HAPS FPGA prototyping hardware, so it can optimize logic placement and partitioning, even on designs with up to 250m ASIC gates.

The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.

The 10nm generation is the follow-on process to the 14nm/16nm node and will provide a choice of either finFET or planar FD-SOI architectures. But the likely absence of EUV will increase costs.