EDA Topics

A look under the hood of IC Compiler II, Synopsys' next-generation netlist-to-GDSII implementation system.

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.

Soft blocking to prevent cell spreading and other placement-optimization techniques helped improve power and clock speed on a Cortex-M7 test chip designed by ARM and Cadence.

A look at a tool and a flow that makes it easier to put designs on to a HAPS physical prototyping system for verification, debug and software development purposes

FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.

ARM and TSMC used an extensive pre-planning process, including a static analysis of each module's overall logic structure, to put together a 2.3GHz processor design based around ARM's main 64bit Big.Little pairing for the foundry's 16nm finFET process.

Lint is no longer just about checking RTL code. It already incorporates functional verification within a three-stage analysis. Time to look again at a 'familiar' technology.

How tuning a design flow can help optimize SoC processor cores for power, performance and area - and make it possible to do different optimisations for different cores on the same SoC.

Innovation in physical verification is driven by incoming nodes but new tools and features can and should be fed back up the technology chain.

How EDA tools are evolving to make it possible to design with finFET processes.