Verifying clock domain crossings when using fast-to-slow clocks
A look at three techniques to verify the validity of signals moving between clock domains
EDA Topics
Fixing late ECOs in ARM core subsystems at STMicroelectronics
Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
Achieving safety and security in SoC development
Designers will have to update development processes to achieve the rigorous safety certifications required in automotive, rail, avionics and similar markets
Putting emulation on the map
Emulation is now served by all three leading vendors and is a hot topic for discussion among engineers. The major verification conferences need to follow suit.
Enabling FPGA prototyping of large ASIC and SoC designs
How tool parallelism, automatic partitioning, deep debug memories and time domain multiplexing eases FPGA prototyping of large ASIC and SoC designs
Developing and integrating configurable GPU IP using FPGA-based prototyping
How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
A better method for early and accurate power estimation
Early and accurate SoC power estimation is possible, says Broadcom, thanks to a technique that maps simulation results between gate and RTL representations
A review of model development for 10nm lithography
John Sturtevant looks at ongoing preparations for the incoming node and charts significant progress that has already been made.
Design reaches out from the edge
We are moving towards a "continuum of compute", ARM CEO Simon Segars said at CDNLive Silicon Valley, a trend that will reshape design.
DO-254 without tears
Compliance with aviation’s hardware design standard is seen as a ‘tough ask’, but EDA’s own evolution has made that process easier than you may think.