January 7, 2019
Escape formal's narrower definitions with a flow that shows you how to Avoid, Detect, Erase, Prove Absence and Tape Out while avoiding bugs.
August 28, 2016
Three senior verification specialists talk about how they are navigating the challenge of verifying multibillion-transistor SoCs with limited compute resource, increasing coverage demands and shrinking timescales.
May 30, 2016
Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.
December 16, 2015
Traditional approaches do not catch all unknown state sources, lack capacity for big SoCs and mask bugs. Ascent XV addresses and overcomes these issues.
July 20, 2014
The argument for an integrated approach to SoC verification
July 3, 2014
How Wall Street's vastly resourced IT teams already point the way to cheaper, faster and more efficient verification by putting goals not tools first.
May 28, 2014
As designs get larger and stress the ability of simulation to exercise an SoC, formal techniques have become essential parts of design and verification.
April 16, 2014
Reset is no longer simply an 'X' issue but also feeds into power optimization. Catching issues early greatly speeds verification.
February 26, 2014
Catching x-propagation issues at RTL saves time and reduces uncertainty in gate-level verification
October 31, 2013
X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.