CAA is a valuable tool available to both design engineers and foundries to help them avoid layout-dependent effects during manufacturing.
Automated voltage-aware DRC addresses the reliability verification challenges in today’s high-voltage and multiple power domain applications.
Machine learning techniques help ensure the validity of Liberty Variation Format information for OCV analysis at lower process nodes.
How to achieve efficient merging of data from formats such as OASIS, GDS, and OpenAccess to ensure timely verification through DRC runs.
A detailed dive into how MBH strategies for litho hotspots have been enhanced to deal with double patterning at 20nm and below.
Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Dina Medhat describes what you need to know about the types of waiver strategy that can be applied.
The authors descirbe a new signature-based approach to resolving the content of layouts in GDSII, OASIS and other formats.
Why design data integrity matters from cell design to tapeout. These techniques will help ensure your validation process is as comprehensive as possible.
Insights from research into reliability at Imec led to self-learning chips, security technologies, and finFET biosensors.
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