Standard physical verification (PV) check reviews within EDA tools can reduce time-to-tapeout and mitigate risk.
We have the technology. Learn how to 'shift left' with Calibre DesignEnhancer and meet IR, EM and PPA objectives.
You must understand six comparison concerns and their effect on database equivalency. Adopt a solution with an in-depth object-based approach.
Learn more about the five interconnected workflows that are democratizing next generation design in the emerging chiplet age.
3D-IC presents major connectivity challenges in maintaining a golden netlist and managing necessary exceptions. Learn how to manage them.
Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
What are the options and how do you balance overarching CAD requirements and personal preferences?
More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
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