3D-IC presents major connectivity challenges in maintaining a golden netlist and managing necessary exceptions. Learn how to manage them.
Coordinate-based checking provides a streamlined way to verify designs around ESD before full-chip runs without the need for custom checks.
What are the options and how do you balance overarching CAD requirements and personal preferences?
More optimistic about the semiconductor industries prospects than for some time, Siemens Joe Sawicki identified key EDA challenges at DAC.
Pre- and post-processing EDA techniques help streamline design rule checks and delivery efficient waivers to speed design and debug.
Delivering physical implementations at new process nodes is getting ever harder. Learn how to stay on track by checking work is rule-compliant as you go.
How to carry out a sensible analysis of cloud EDA's potential, so you get the right tools and computational resources to deliver increasingly complex designs.
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
Reliability rule checks need - and now get - more granular analysis that allows designers to adopt proposed waivers with much greater confidence.
For physical verification and beyond, each process node requires new thinking, new tools and greater performance.
View All Sponsors