May 26, 2014
In the absence of EUV lithography, the primary option for manufacturing on a 10nm process is to extend double patterning. But the options each have issues.
January 13, 2014
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
January 13, 2014
Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.
August 21, 2012
A guide to emerging 3D integration techniques for ICs, including a look at various approaches, and some of the tools and standards issues involved.
March 28, 2012
It may be necessary to move to three-dimensional 'FinFET' transistors for future process nodes, but what impact will this have on circuit design?
March 28, 2012
Fully depleted silicon on insulator (FD-SOI) transistor architectures may offer speed and power advantages, at the cost of a shift to non-standard substrates.
January 16, 2012
Double patterning provides an alternative to using EUV lithography – making it possible to implement ICs on sub-28nm processes.