multi-patterning

October 21, 2021
Sherif Hany Mousa is a Principal Technologist in the Calibre Design Solutions division of Siemens EDA, a part of Siemens Digital Industries Software. Sherif previously held positions as a technical marketing engineer, analog quality assurance engineer, and IC design consultant for physical verification and analog/mixed signal applications. He has authored multiple publications and holds multiple patents in the fields of analog layout porting, hotspot detection and correction, and machine learning-assisted verification flows. Sherif is a senior IEEE member who holds an M.Sc. in Electrical and Communication Engineering, and is currently engaged in Ph.D. research, focusing on circuit analysis.

Advanced symmetry verification is a thing of beauty

Innovation is extending the technique's power across areas such as context-aware layout, accounting for multi-patterning and implementing fill.
Expert Insight  |  Topics: EDA - IC Implementation, Verification  |  Tags: , , , , ,   |  Organizations:
May 31, 2021
Srinivas Velivala is a principal product manager with Calibre Design Solutions in Siemens EDA, a part of Siemens Digital Industries Software. His primary focus is the development of Calibre integration and interface tools and technologies. Before joining Siemens EDA, he designed high-density SRAM compilers. In addition to more than 12 years of design and product management experience, Srinivas holds a B.S. and M.S. in Electrical and Computer Engineering.

How you can decide what level of DRC you need when you need it

Using on-demand rule checks during place-and-route boosts efficiency and design quality.
September 11, 2018
Gandharv Bhatara is the product marketing manager for the Calibre OPC/RET products at Mentor, a Siemens Business.

EUV’s arrival demands a new resolution enhancement flow

Gandharv Bhatara looks at how the OPC and RET elements of Calibre are getting ready for the EUV age.
Expert Insight  |  Topics: EDA - DFM, - EDA Topics  |  Tags: , , , , , , ,   |  Organizations: , ,
November 24, 2017
John Ferguson is the Director of Marketing for Calibre DRC Applications at Mentor, a Siemens Business, in Wilsonville, Oregon, with extensive experience in physical design verification. He holds a BS degree in Physics from McGill University, an MS in Applied Physics from the University of Massachusetts, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

Assessing the true cost of node transitions

John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
October 27, 2017
Featured image - double patterning at advanced nodes

Catch multi-patterning errors clearly at advanced nodes

How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Article  |  Topics: EDA - DFM, - EDA Topics, EDA - Verification  |  Tags: , , , , , ,   |  Organizations:
October 3, 2016
Place and route beyond 10nm

How place and route is adapting to challenges below 10nm

Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
November 26, 2015
Cadence mask coloring assistant

Mixed-signal designs prepare for coloring at 10nm

The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.
August 12, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Sign-off lithography simulation and multi-patterning must play well together

Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.

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