double patterning

October 27, 2017
Featured image - double patterning at advanced nodes

Catch multi-patterning errors clearly at advanced nodes

How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
Article  |  Topics: EDA - DFM, - EDA Topics, EDA - Verification  |  Tags: , , , , , ,   |  Organizations:
October 3, 2016
Place and route beyond 10nm

How place and route is adapting to challenges below 10nm

Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
October 29, 2015
Innovus chip layout

Cadence’s path to digital implementation on 10nm

The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.
July 20, 2015
TSMC finFET

Lessons learned in the finFET trenches

In sessions at the 2015 Design Automation Conference, engineers who had worked on finFET-oriented projects revealed how the technology has changed their design practices and where others may want to think twice about making the move.
August 12, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Sign-off lithography simulation and multi-patterning must play well together

Sign-off lithography verification is vital as we move beyond double to multi-patterning but changing responsibilities in the flow must be handed with care.
January 20, 2014
Jean-Marie Brunet is the Product Marketing Director for DFM at Mentor Graphics

Patterning choices loom for 10nm and beyond

It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
January 13, 2014
Steffen Schulze is director of marketing for Calibre Mask Data Preparation at Mentor Graphics

Consider your options for future nodes

If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.
December 3, 2013
Dr David M Fried is Chief Technology Officer - Semiconductor at Coventor, responsible for the company’s strategic direction and implementation of its SEMulator3D Virtual Fabrication Platform.

Lithography challenges threaten the cost benefits of IC scaling

The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
Expert Insight  |  Topics: EDA - DFM  |  Tags: , , , , , , , , ,   |  Organizations:
August 25, 2013
Tim Whitfield, director of engineering, ARM Taiwan

Proving the 20nm ecosystem with the ARM Mali GPU

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
April 22, 2013
Layout segment showing problem of color splitting with double patterning

The five key challenges of sub-28nm custom and analog design

The arrival of the 20nm and finFET-based 14nm and 16nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors