Patterning choices loom for 10nm and beyond
The next few process nodes present major challenges to SoC design teams in terms of manufacturability. Extreme ultraviolet (EUV) was, at one point, the leading contender for the 14nm and 10nm nodes but this looks increasingly unlikely. So the industry is examining various options and calculating the effect on design as well as production cost.
So far, the industry has adopted double patterning to ensure it can continue to use 193nm lithography tools. The bulk of the SoC industry today focuses on some form of double patterning – such as litho-etch, litho-etch (LELE) — in which the design is split into two complementary mask that are exposed and processed separately to create a single layer of on-chip features. Double patterning may not provide enough resolution for the 10nm node, so manufacturers are looking at ways to extend the LELE concept to triple and, for more advanced products, even quadruple patterning. But LELE is not the only potential solution.
Self-aligned multiple patterning (SAMP) uses chemical techniques, conceptually similar to those that have been used for decades, to deposit materials on the gate stack with extremely tight critical dimension (CD) control. With SAMP, a single mask is exposed and a sequence of deposition and etch steps are used to “pitch split” the design. Instead of producing a single line of resist, two or more lines are created that run in parallel. In effect, you get several lines almost for the price of one.
An extension of SAMP is directed self-assembly (DSA), which uses materials such as block copolymers to deposit an array of simple shapes in an area defined by a mask. Although a younger technology – self-aligned double patterning is already in use in some fabs – DSA is being actively investigated and shows promise as a way of providing high-resolution features that are difficult or expensive to yield using other techniques. But, like SAMP, the link between design and the DSA-based mask is far less clear than it is for the split LELE masks. Designs that make use of SAMP or DSA will be even more heavily constrained in terms of what are considered valid designs than with LELE. SAMP, for example, favors “one dimensional” designs in which the features on a given layer all run in parallel. Circuit lines are defined simply by cutting lines and connecting them through vias to partner lines on an upper or lower layer.
One-dimensional design has an impact on design density – the benefit in manufacturing cost may not justify this loss of density compared to LELE. However, that does not rule out the use of SAMP or, indeed, DSA in tomorrow’s production flows.
The patterns favored by SAMP may fit the profile of polysilicon and local-routing layers, while LELE mask sets are likely to be a better fit for high-density metal layers. By making it possible to deposit arrays of simple shapes, such as contact holes, DSA may prove to be an effective method of defining via and contact layers. The ability to deposit arrays may prove to be a way of overcoming overlay issues, with redundant features used to ensure good connection on paths even if CD control cannot be guaranteed.
There will be other impacts on DFM. Density balancing becomes more complex with triple patterning to ensure that each mask has an appropriate amount of fill to ensure consistent process control. Similar techniques may be needed for self-aligned technologies to ensure consistent process control across the die.
At this stage, it is difficult to see which way the industry will move. But everyone in the supply chain needs to be ready for when those decisions are made, and be armed with the data needed to support effective DFM flows. This is why Mentor is working to model the impact each of these process options will have, not just on manufacturability, but also on design.