Parasitic extraction tools help designers understand how physical implementation will impact the behavior of their ideal logic and circuits, by analyzing the layout of their design and calculating the unwanted (or parasitic) resistances, capacitances, and (possibly) inductances that have been introduced by connecting real devices in close proximity to each other with real wiring run on multiple layers. The resultant values are used to calculate:
- how signals will propagate, to ensure signals will meet the timing necessary for the chip to function as designed
- how noise is coupled from one element to another
- IR drop on longer lines, to ensure that, especially in advanced processes with low supply voltages, the whole chip will be properly powered
- and how devices will behave on the finished chip
Current challenges in parasitic extraction
Parasitic extraction is always a trade-off between accuracy and computing resources. As processes become more dense, finding the trade-off is becoming more difficult because the processes are becoming more complex, and because the average design uses more gates. Here are some of the key issues in parasitic extraction:
Increasing interconnect resistance
The resistance of interconnect has been steadily rising per unit length at each new process node, as the cross-section of wiring has shrunk. Extra metal layers have been introduced to ensure there is enough routing resource on these denser processes. The result is that interconnect has gradually changed shape, from a square to a tall, narrow rectangular cross-section, to accommodate as much wiring as possible on each layer while trying to maintain the same resistance. Nonetheless, interconnect resistance has been rising, as has the lateral coupling between lines. The result has been increased RC delay, which designers are trying to work around by moving critical signals to higher levels of the metal stack using layer-aware routing.
Dummy fill, areas of unconnected poly or metallisation, is increasingly used to even out the impact of various manufacturing steps and ensure the physical planarity of the final chip. Each fill area adds to the number of elements that the extraction process has to consider, as well as the complexity of the possible interactions between them and circuit elements.
Double and multi-patterning
Double patterning was introduced at the 20nm node to overcome the resolution limits of immersion lithography systems working with 193nm illumination. The technique involves spitting features on the densest layers across two masks so that each can be patterned separately, within the lithographic limit. The drawback to double patterning (along with its cost and complexity) is that any misalignment between the two masks introduces geometric variability, which causes the parasitics to vary. Some foundries have already modelled this issue to analyze the design impact of mask misalignment. Two broad approaches have been tried. In the first, designers move one mask relative to the other by a specific amount and in a specific direction and then see what impact that has on the parasitics. Multiple shifts are necessary to find the worst-case impact of mask misalignment per double-patterned layer. In the second approach, the mask misalignment is modelled as a change in dielectric constant, on the basis that both sides of a misalignment will increase or decrease their capacitance in the same way. The drawback of this approach is that it may be too pessimistic. How much does this matter? One analysis suggests that, compared to perfectly aligned masks in a 20nm process, a 2nm offset could have a 5% impact on coupling capacitance values, while a 6nm shift could result in differences as high as 20%.
The shift to finFETs
Planar transistors leak too much at nodes below 20nm, so the industry has introduced finFETs to counter this problem by moving the channel out of the bulk into a ridge on its surface. Designing with finFETs reduces leakage and improves drive current, at the cost of using a more complex structure that has to be modelled in a more complex way with three or four times as many parasitics per transistor than for a planar device. The introduction of finFETs has also brought with it a more complex local interconnect scheme, known as ‘middle of line’ (MOL) or ‘middle end of line’ (MEOL) to distinguish it from the steps performed during front-end-of-line (FEOL) transistor manufacture and back-end-of-line (BEOL) metal interconnect construction. The close proximity of MOL local interconnect to the vertical transistor fins and the more complex shapes it involves as it wraps around the source and drain increases the complexity of calculating parasitics. The finFET’s higher drive strength and increased gate capacitance (compared to planar devices) mean that IR and EM analysis, based on accurate parasitic extraction, is increasingly important to ensure reliability. FinFETs are also subject to new effects such as device width quantization (you can only increase the device width by adding whole fins), which makes transistor models more complex. The fact that finFETs rely on local stressors to improve their performance means that their context within a layout also has to be taken into account.
As processes shrink, the impact of variability becomes more acute. Mask misalignment is one of these. Other manufacturing issues such as overlay alignment, as detailed here, compound the problem. Foundries and fabless companies alike are concerned about the impact of variability on the practical benefits of moving to finFET processes. With manufacturing margins so tight, excess variability in the processes could absorb some of the advantages of these more complex processes. The same is true of the accuracy with which parasitics are extracted, which is why foundries and others are calling for greater accuracy from parasitic-extraction and simulation tools.
While process complexity and design size are rising, so is the demand for increased extraction accuracy. This is challenging tool vendors to come up with better ways of extracting parasitics, greater accuracy in extraction, better modeling techniques to ensure that all the relevant parasitics are correctly calculated, and ways of increasing overall extraction capacity and performance.
Tool and technique responses
Parasitic extraction can be carried out at the transistor level, to achieve the most detailed understanding of how circuits perform, or at the cell level to improve speed and capacity at the cost of giving up some accuracy. One way to ease the pressure on the transistor-level extraction process caused by the greater complexity of finFETs is to standardise the way that devices are modelled. Modeling finFETs accurately means adding information to represent source/drain resistance extensions, contact resistances, fringing effects and the coupling capacitances introduced by the 3D nature of the device. Fortunately the BSIM Group has defined a standardized model for use in SPICE simulators, known as the Berkeley Short-channel IGFET Model for Common Multi-Gate (BSIM-CMG) compact model. This gives engineers a standard way to define their device, with placeholders for its key values. It is also important to work out which parasitics relating to a device don’t vary with its context in the layout, and so belong in the FEOL SPICE models, and which are changed by the layout and so belong in the MEOL models. Not being clear where each parasitic should be described could lead to double-counting, or to important parasitics not being accounted for properly.
Parasitic extraction is usually run at multiple ‘design corners’, that is combinations of operating characteristics, to check that a design will meet its timing goals in all circumstances. For a long time, designs were checked at five basic corners, but this has risen to 15 in some cases, to take account of increasing manufacturing and circuit variability. Running multiple extractions takes extra time, and so some vendors have introduced simultaneous multi-corner extraction, which reduces the redundant work involved in multiple extractions. Speed-ups of three to five-fold are claimed, compared to a sequence of single-corner extractions. Vendors are also using parallelism to speed up extraction, finding ways to distribute the work of analysing large layouts at multiple design corners across multiple threads and multiple CPUs.
Parasitic extraction necessarily involves simplifications – it isn’t possible to run a full 3D solution, using Maxwell’s equations, to derive all the parasitic values for a complete chip. However, vendors are now making it easier to substitute values from a full 3D solver into the extraction process for selected critical features, gaining accuracy without incurring a runtime penalty.
Extraction in 3DIC design
Parasitic extraction will also play an increasing role as designers explore ways of integrating more functionality by connecting die on top of each other in 2.5 or 3DIC arrangements, or even as monolithic 3D ICs. Parasitic extraction will be needed to understand and model the complex interconnect schemes used in these integration strategies, to ensure that timing requirements can be met even taking into account factors such as microbump-to-pillar parasitics, coupling between bumps and the top routing level of the lower die, and so on. Strategies for tackling this complex issue are already in development.