10nm

May 28, 2015

Dynamic power optimization

FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
May 19, 2014

10nm processes

The 10nm generation is the follow-on process to the 14nm/16nm node and will provide a choice of either finFET or planar FD-SOI architectures. But the likely absence of EUV will increase costs.

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