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May 19, 2014
10nm processes
The 10nm generation is the follow-on process to the 14nm/16nm node and will provide a choice of either finFET or planar FD-SOI architectures. But the likely absence of EUV will increase costs.
Guide | Topics:
EDA - IC Implementation
| Tags:
10nm
,
1D design
,
cell pin access
,
directed self-assembly
,
interconnect resistance
,
SAMP
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DFM
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