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Chips & Media
Chips & Media
April 2, 2019
High-level synthesis for AI: Part Two
How Chips&Media used HLS on the development of a computer vision IP block.
Expert Insight | Topics:
EDA - ESL
,
IC Implementation
| Tags:
AI
,
algorithm
,
architectural exploration
,
artificial intelligence
,
C++
,
computer vision
,
deep neural networks
,
DNN
,
high-level synthesis (HLS)
,
hls
,
IP
,
RTL
| Organizations:
Chips & Media
,
Siemens EDA
,
TensorFlow
EDA Topics
DFM
DFT
ESL
IC Implementation
Verification
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