FPGA

June 2, 2020
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

VHDL users also deserve efficient design and verification

More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
Expert Insight  |  Topics: EDA Topics, EDA - Verification  |  Tags: , , ,   |  Organizations:
March 26, 2019

High-level synthesis for AI: Part One

The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
February 12, 2013

How virtual prototyping enabled Altera’s SoC FPGAs

The technique drove ‘agile systems development’ for the programmable logic vendor’s new product line.
Article  |  Topics: Embedded - Architecture & Design, - Embedded Topics  |  Tags: , ,   |  Organizations: ,
October 25, 2012

Vivado HLS/AutoESL: Agilent packet engine case study

How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine
October 23, 2012

Vivado, inside the new Xilinx design suite

The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
July 5, 2012

Improving ASIC prototyping on multiple FPGAs through better partitioning

Using a new design-partitioning tool and stacked-silicon interconnect FPGA to develop an ASIC prototyping platform that can be reprogrammed several times a day.
Article  |  Topics: EDA - DFM  |  Tags: , , ,   |  Organizations: ,
April 5, 2012

FPGA prototyping

Building a prototype SoC in one or a set of FPGAs can aid field trials, software development and hardware/software integration. But it's not easy, so the decision to go ahead needs careful consideration.
June 2, 2011

Strategic considerations for emerging SoC FPGAs

This white paper describes the emergence of SoC FPGAs, the drivers behind their market, and proposes some strategic considerations for executive management and system designers when choosing these devices.
Article  |  Topics: EDA - DFT  |  Tags: ,
December 14, 2010

Achieving teraflops performance with 28nm FPGAs

FPGA-based signal processing has traditionally been implemented using fixed-point operations, but high-performance floating-point signal processing can now be implemented. This paper describes how floating-point technology for FPGAs can deliver processing rates of one tril- lion floating-point operations per second (teraflops) on a single die.
Article  |  Topics: EDA - DFT  |  Tags:
June 1, 2010

Device native debug and verification for FPGA

GateRocket's RocketDrive facilitates integration of an FPGA into an HDL simulator to provide a "native" execution of a design on its target FPGA device. The companion RocketVision tool provides software-debugging capabilities that directly identify and enable the rapid resolution of bugs. This article considers the use of these tools in a "device native" verification and [...]
Article  |  Topics: EDA - Verification  |  Tags: , ,

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