More commonly associated with SystemVerilog, IDEs can also greatly help users of the popular HDL for FPGA, mil/aero and other designs.
The computational and algorithmic demands made by computer vision systems highlight HLS' value for AI system development.
The technique drove ‘agile systems development’ for the programmable logic vendor’s new product line.
How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine
The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
Using a new design-partitioning tool and stacked-silicon interconnect FPGA to develop an ASIC prototyping platform that can be reprogrammed several times a day.
Building a prototype SoC in one or a set of FPGAs can aid field trials, software development and hardware/software integration. But it's not easy, so the decision to go ahead needs careful consideration.
This white paper describes the emergence of SoC FPGAs, the drivers behind their market, and proposes some strategic considerations for executive management and system designers when choosing these devices.
FPGA-based signal processing has traditionally been implemented using fixed-point operations, but high-performance floating-point signal processing can now be implemented. This paper describes how floating-point technology for FPGAs can deliver processing rates of one tril- lion floating-point operations per second (teraflops) on a single die.
GateRocket's RocketDrive facilitates integration of an FPGA into an HDL simulator to provide a "native" execution of a design on its target FPGA device. The companion RocketVision tool provides software-debugging capabilities that directly identify and enable the rapid resolution of bugs. This article considers the use of these tools in a "device native" verification and [...]
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