EDA

John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.

Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques such as clock gating or register re-timing.

The challenge for designers is to find ways of providing high levels of security in low-cost devices that have become worthwhile targets because of their role as gateways to more valuable information.

How emulation was used to debug out-of-spec power on a multicore ARM design using the AXI bus.

How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.

The COM methodology is being extended and more widely adopted across high-speed designs thanks to deeper tool integration.

The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.

Using USB Type-C connectors to combine both USB-C 3.1 and DisplayPort data streams, to support data, audio, video and power connections on a single port

Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.

An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.