EDA

High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.

Doc Formal concludes his introduction to formal verification with a practitioner's view of the technology.

Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.

Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.

This introduction to the new Accellera standard includes a demo of portable stimulus in use to fully verify a DMA engine.

Doc Formal begins a two-part series by describing the solid and well-established foundations of formal verification.

CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.

Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity.

Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.

SoC developers who want to use USB Type-C in their designs will have to implement HDCP 2.2 content protection so that the target devices will be able to play protected content.