How Channel Operating Margin helps Gigabit Ethernet PCB analysis
The COM methodology is being extended and more widely adopted across high-speed designs thanks to deeper tool integration.
Channel Operating Margin (COM) is an emerging algorithm-based methodology for ensuring compliance in high-speed designs. More than 200 companies already support COM, including infrastructure suppliers like Ericsson, connector suppliers like Molex and EDA vendors like Mentor, a Siemens Business.
So if you are working in areas such as Gigabit Ethernet – particularly beyond 25Gbit/s – or associated areas like SERDES, you are probably already looking at its basics. However, supporters are looking to extend COM’s ideas to other high-speed design segments. COM should now start to reach a wider audience.
The Channel Operating Margin has emerged as the compliance challenge became more complex at increasing data rates. Around 1-3Gbit/s, eye diagrams based on device speed were broadly sufficient. With the move to 3-8Gbit/s some equalization was needed to meet the eye mask requirements. Further tweaks and metrics came at 10Gbit/s.
At 25-28Gbit/s, compliance through COM is achieved by bundling these existing techniques alongside an algorithmic analysis of the transmitter, the receiver and the channel. To accommodate this framework, some minimum architectural requirements have been set for Tx and Rx.
Put simply, you break down the challenge into the driver, the receiver and the channel – the channel being the traces, vias and structures on a PCB.
How to apply Channel Operating Margin
The fundamentals of the Channel Operating Margin have been written into the 100Gigabit Ethernet Interface standard, IEEE 802.3bj (Annex 93), though the technique continues to evolve.
As a rule of thumb, you want to be able to run COM as a black box based on a series of S-parameters. COM will consider these and also factors such as jitter, noise and models for SERDES responsiveness. It will then deliver a figure of merit in dB. For a typical pass, the designer is looking to exceed a threshold value of ‘3’ (for most operating modes) or greater for a ‘pass’ – indeed, the greater the dB value returned, the more robust the design.
This sounds like a complex task has been made far easier, and COM’s existing users say it has the further benefit of reducing the amount of overdesign previously required to achieve high-speed compliance.
Mentor was the first EDA company to incorporated COM algorithmic analysis in a PCB analysis suite, Hyperlynx. The company has also been contributing to the improvement of the algorithm through a number of DesignCon papers.
Mentor has integrated Channel Operating Margin within its Hyperlynx PCB analysis suite (Mentor)
The fully integrated and automated flow ranges from s-parameters extraction to post-processing, in both pre- and post-layout environments. All the IEEE and OIF-CEI specifications are supported including those that are still in development (i.e. IEEE802.3bs, IEEE8023.cd and OIF-CEI-04.0). An online seminar shows how easy and straightforward it is to run.
The Channel Operating Margin’s evolution continues
Given all this, the Channel Operating Margin is extending further to support its use to check compliance in the 53Gbit/s 400Gigabit Ethernet standard for both Non-Return-To-Zero (NRZ) and multiplexed Pulse Amplitude Modulation (i.e. PAM-4).
Individual vendors, including Mentor, are also looking at ways to build on the core standard COM to offer greater accuracy.
As COM develops, an increasing amount of collateral is appearing to support its use. For those of you ready to take a deeper dive, here are a couple of recommendations.
Anritsu has published a thorough overview of the technology, including some thoughts on how it harmonizes results.
Mentor has posted the winner of the best paper award at DesignCon 2016, ‘BER and COM Channel Compliance’. It analyzes the computational procedure specified for COM and compares it to traditional statistical eye/BER analysis.
