IMEC stacks nanowire transistors together on CMOS
IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked nanowire transistors.
Archives
Overcoming electromigration analysis limitations for larger on-die power grids
Award-winning paper describes new strategy offering both greater speed and accuracy.
HiSilicon licenses onchip debug engine for SOCs
HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
Security group publishes first guidelines
The UK's IoT Security Foundation has published the first set of documents intended to provide best-practice guidelines for developers of embedded systems.
Codasip adopts UltrasSoC debug for RISC-V cores
Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
Siemens agrees deal to buy Mentor Graphics
German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.
Multicore Association to update performance-estimation standard
The Multicore Association has started work on the second version of its SHIM performance-modeling standard for SoCs.
Webinar focuses on Eldo RF verification of Tanner-based designs
On-demand seminar explains how to exploit recently announced integration of Tanner and Eldo suites for sensor, IoT and other design types.
Multicore standard works on fast communications
Work by the Multicore Association to provide a standard way for applications running on different processors to communicate with each other is leading to active implementations.
Cadence maps out safety plan for semiconductor-design tools
Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.