Goodbye to the mixed-signal black box
There are some inescapable truths in electronics design: The more challenges we overcome, the more we want to confront new ones and topple them.
Today, we know, the level of complexity for most designs is staggering. To achieve our cost and form factor design goals, we are deep into the era of mixed-signal design and system integration. Complex systems-on-chip (SoC) not only have to include blocks of digital and analog circuits, but they must be verified now together, not separately.
The prior methodologies of integrating and verifying this IP – black box IP, whether digital or analog – is no more because engineers must understand the functionality of the complete system, including how each “black box” is interacting with its neighbors and the larger system.
In the relentless pursuit of better design and verification methodologies coupled with shrinking design-cycles, real-number modeling is emerging as a smart verification choice within the spectrum of verification methods (see Figure 1), from accurate-but-slow SPICE simulation to faster-but-less-accurate RTL modeling (Verilog-AMS, VHDL-AMS, and so on).
Figure 1 The tradeoff in accuracy and speed in mixed-signal simulation (Source: Cadence)
And thanks to the February ratification of IEEE 1800-2012 (SystemVerilog), real-number modeling takes on a greater and more accessible role in verification.
“We’re enabling system-level engineers to integrate robust and more accurately abstracted real number models,” said Sathishkumar Balasubramanian, senior manager of strategic initiatives within Cadence’s Chief Strategy Office. “Cadence has contributed to the standard, and we’re among the first to support the standard.”
Balasubramanian said Cadence has supported many of the capabilities in this standard before in other modeling languages, such as Verilog-AMS. And now Virtuoso supports the latest IEEE-ratified aspects of real-number modeling.
“Now engineers who are using Verilog-AMS will have a smoother migration path to SystemVerilog real number models and vice versa,” he said, adding, “we’re enabling a different set of users.”
What does he mean by that?
Traditionally, “SoC guys are using digital verification and they’re using mainly SystemVerilog as a go-to standard to write the full chip verification,” Balasubramanian said.
Real number modeling with System Verilog and other languages allows the simulation of discrete, floating-point real numbers that can represent analog behavior which, for example, could be voltage, current and/or impedance. RNM enables users to describe an analog block as a signal flow model, and then simulate it in a digital solver at near-digital simulation speeds.
For analog and mixed-signal block verification, RNM can be used to speed high-frequency portions of the analog signal path-which take the longest to verify in simulation-while DC bias and low-frequency portions remain in SPICE.
“The real advantage,” Balasubramanian said, “is RNM enables in top-level SoC verification, where engineers can represent all electrical signals as RNM equivalents and stay within the digital simulation environment.”
In February, IEEE ratified IEEE 1800-2012, which melded the best features of VHDL and Verilog-AMS real-number modeling into SystemVerilog.
The new features in the standard overcome issues with prior versions of SystemVerilog (2009 and prior LRM) by enabling:
- Real number nets
- Bi-directional real connections
- Multiple RNM contributors to the same net
- Modeling complex information on a single net (eg. voltage and current)
While the ratified standard is relatively new, it’s being embraced already by users, like thirsty hikers rushing to a stream. The importance of what real-number modeling enables for verification teams probably can’t be overstated.
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