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post-silicon debug
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June 9, 2014
Applications won’t find all the bugs, but they have their uses
Can applications provide useful input for verification? They can but not when run straight out of the box, panelists at DAC 2014 said.
Article | Topics:
Blog - EDA
,
Embedded
| Tags:
DAC 2014
,
deadlock
,
debug
,
ESL
,
functional verification
,
multicore
,
network-on-chip
,
post-silicon debug
,
software-driven verification
,
verification coverage
| Organizations:
Arm
,
Green Hills Software
,
IBM
,
Jasper Design
,
Mentor Graphics
October 9, 2013
Jasper preps User Group and Architectural events
The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
Article | Topics:
Blog Topics
,
Conferences
| Tags:
low power
,
post-silicon debug
,
validation
,
verification
,
verification IP
| Organizations:
Jasper Design
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