DATE notebook: Forget automation, give us acceleration

By Chris Edwards |  No Comments  |  Posted: March 13, 2012
Topics/Categories: Commentary, Conferences, Digital/analog implementation, Blog - EDA  |  Tags: , ,

Ciaran Whyte, cofounder and chief technical officer of Ireland-based design house IC Mask Design, had a simple message in a panel at Design Automation and Test in Europe (DATE) for those wanting more automation to try to push analog designers past their current average productivity of one device an hour: stop trying to push automation in design tools; instead give users better acceleration features.

“Companies like Cadence have come up with automatic layout tools but they had have next to no traction. Productivity comes in analog design not in automation but in acceleration.”

Many of the analog layout tools support scripting and this has been used by many designers to take the legwork out of drawing multifingered transistors and other complex shapes that take a long time to produce by hand but which can be expressed readily with a script. Whyte argued that it’s possible to build some more smarts into these scripts and use them to generate more complex parameterized shapes and subcircuits.

“Every single analog circuit will have a voltage divider, for example. We can take these and move them into super-parameterized cells.”

Whyte said IC Mask has done its own scripts to do this kind of work and argued that this is different to layout automation because the engineer is in control of what gets generated: they choose their favored architecture for a job and then tell the tool to produce one of a given size. He added that even constraint-driven design, which in some ways follows this approach, has not worked because it forces the designer to change methodologies, which they do not want to do. The acceleration approach keeps the same overall approach of pushing polygons, but the machine is doing a lot more of the pushing.

Georges Gielen of the Catholic University of Leuven argued there is place for automation, or at least optimization. “Over the years there has been a lot of progress in developing what I would call a circuit and layout optimization capability. This capability is ideally suited for fine tuning and cranking the last milliwant out of a circuit, and also for porting from one generation of a process to another.”

Click here for more of our coverage of DATE 2012


Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors