Debug life cycle expands with on-chip infrastructure
By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
Author Archives: Chris Edwards
Cloud EDA service gears up for commercial projects
Silicon Cloud is preparing to expand access to its network-based design environment beyond the universities using it today to commercial users
Smart lenses getting closer to live use
Google has moved to on-body tests of the the smart-lens platform it has been developing for the past few years while the team continues to experiment with embedded LEDs that react to blinks to help warn diabetes sufferers of sudden changes in glucose levels.
Formal integration enhances bug-hunting for Cadence
Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.
Altera boosts density and pipelining in finFET FPGA shift
Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.
DTCO tool aims to squeeze more out of older processes
Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.
S3 aims at MIMO WiFi with smaller ADC core
S3 Group has launched the second in a family of low-power successive-approximation ADCs, with a design that supports sample rates up to 320MS/s.
Speedy software creation to show off custom-tool possibilities
Invionics will be using its software environment to create a custom tool within just two days at the 52nd DAC.
OneSpin brings formal to bear on ISO 26262 fault tracing
OneSpin Solutions has used its formal-verification technology as the basis for an app intended for ISO 26262 projects that analyzes the ability of a design to deal with fault conditions.
Docea adds API to model power software interactions
Docea Power has added a programming interface to the latest version of its Aceplorer power-modeling software to show how chipset designs would fare under a variety of software-based power-management algorithms.