EDA

Startup launches an analog-circuit migration and optimization tool that uses less simulation time than traditional approaches the company claims.

Menta SAS has launched an embedded FPGA core family that improves density over previous versions.

Concept Engineering is introducing a version of its Nlview family of automatic schematic generation products that runs inside a standard web browser.

Samsung Foundry has adapted Mentor's DFM and test tools in a system that can produce a 10% increase in yield across all nodes.

Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.

The company's annual 'What to see' list is now available for download and highlights some of EDA's less recognized areas of innovation.

Ansys has decided to marry cloud computing with some of the tools used in SoC design that can make use of large amounts of temporary computer power.

ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.

Videos detail techniques to improve the functional safety and reliability of FPGA designs, including the implementation of triple modular redundancy, safe FSM schemes and self monitoring.