By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
A look at three design challenges for USB Type-C: implementing two SuperSpeed datapaths on a reversible connector; partitioning the design to support multiple USB Type-C variants; and partitioning the management software.
These days, when it comes to innovation: The car's the star - not the stooge.
How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
Using triple modular redundancy, error detection and correction, and 'safe' FSMs to ensure greater functional safety in FPGA-based designs
Dr Walden Rhines, Mentor Graphics chairman and CEO, looks forward to the trends that will shape 2016 in the semiconductor industry.
The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.
The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.
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