Advanced tools are being applied to established nodes to produce advanced designs for volume markets.
The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.
It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
Increasingly complex design rules in 14nm and 16nm makes it harder to connect local routing to the inputs and outputs (pins) of standard cells.
The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.
Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
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