IC Implementation

June 1, 2016
How Google and Qualcomm use HLS and HLV

How Google and Qualcomm exploit real world HLS and HLV

By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
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May 10, 2016
USB Type C connector

Implementing USB Type-C

A look at three design challenges for USB Type-C: implementing two SuperSpeed datapaths on a reversible connector; partitioning the design to support multiple USB Type-C variants; and partitioning the management software.
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April 26, 2016
Andrew Macleod is Director of Automotive Marketing for Mentor Graphics. He has more than 15 years of experience in the automotive software and semiconductor industry, with expertise in new product development and introduction, product management and global strategy, including a focus on the Chinese auto industry.

Still using Moore’s Law to beat up on the automotive industry?

These days, when it comes to innovation: The car's the star - not the stooge.
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February 22, 2016
ICCII floorplanning article - featimg

Floorplanning complex SoCs with multiple levels of physical hierarchy

How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
February 18, 2016
RTL Floorplanning - Featured Image

How new RTL floorplanning techniques speed physical design

Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
January 11, 2016
FPGA protection featimg

FPGA design for functional safety

Using triple modular redundancy, error detection and correction, and 'safe' FSMs to ensure greater functional safety in FPGA-based designs
January 11, 2016
Dr Walden Rhines is Chairman and CEO of Mentor Graphics

2016 – A continuation of change

Dr Walden Rhines, Mentor Graphics chairman and CEO, looks forward to the trends that will shape 2016 in the semiconductor industry.
January 4, 2016
Interconnect variation in SoC

Timing analysis shifts to statistical

The 10nm process node calls for the use of SOCV techniques during timing signoff to avoid leaving too much performance on the table.
November 26, 2015
Cadence mask coloring assistant

Mixed-signal designs prepare for coloring at 10nm

The arrival of the 10nm process will impact the way that designers approach custom and mixed-signal layout. Cadence Design Systems has made changes to its Virtuoso environment that deploy increased automation support and electrically-aware layout to deal with the upcoming issues.
October 29, 2015
Innovus chip layout

Cadence’s path to digital implementation on 10nm

The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.

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