IC Implementation

April 3, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
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March 27, 2014
Achieving multi-scenario signoff more quickly and predictably using timing-driven ECO

Achieving multi-scenario signoff quickly and predictably using timing-driven ECO

Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
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February 11, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

The new landscape of advanced design

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.
February 6, 2014
Sudhakar Jilla is group marketing director for place & route at Mentor Graphics.

Concurrency tackles MCMM issues head-on

The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
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January 28, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

Are advanced designs only possible at emerging process nodes?

Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.
January 20, 2014
Jean-Marie Brunet is the Product Marketing Director for DFM at Mentor Graphics

Patterning choices loom for 10nm and beyond

It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
January 13, 2014
Interconnect resistance has increased since the 40nm node

Interconnect resistance

A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
January 13, 2014
Multiple patterning is causing issues with access to standard-cell pins in nanometer processes

Cell pin access

Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.
January 7, 2014
Neil Songcuan is a senior product marketing manager, responsible for the FPGA-based Prototyping Solution at Synopsys.

Using HAPS to streamline IP to SoC integration

The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
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December 23, 2013
Featured image Marvell case study

Better management of timing closure and optimization

How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.
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