Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
Better delay estimation of sub-32nm interconnects, in which resistivity varies up to 100x between layers, helps Cavium improve overall performance and get ready for even denser processes
Going inside HLS' basics shows how it can deliver power savings over 50% for some applications.
Problems become expensive to fix after the place-and-route stage so it's time to think seriously about the role of RTL signoff within the design flow.
PGA has been IC-centric for mainstream 2D configurations. It must become system-centric for 2.5D and 3D systems.
Electrically aware layout tools provide a more efficient alternative to time-consuming rip-up-and-retry practices in mixed-signal nanometer IC design.
Build tools around the dataflows and control systems engineers model to address verification challenges posed by burgeoning complexity and low power.
New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
Power intent, signal isolation and level shifting can all be controlled in a UPF-based multi-voltage IC design through careful coding.
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