IC Implementation

May 30, 2015

Clock tree synthesis

Clock-tree generation is coming under increased scrutiny because of its role in dynamic power consumption and problems caused by on-chip PVT variation.
May 28, 2015

Dynamic power optimization

FinFETs present a number of problems with respect to dynamic power consumption. Design techniques are being re-evaluated to deal with the issue.
July 23, 2014

20nm

The 20nm node can offer power, performance and area advantages, but making these gains takes a deep understanding of the interactions between process and design.
July 13, 2014
ST/CEA-Leti 'Frisbee' wide-voltage DSP

DVFS and body bias

Dynamic voltage and frequency scaling is effective for low-power VLSI design. Body or back bias can provide additional control over leakage and performance.
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June 22, 2014
Preview image for monolithic 3D integration

Monolithic 3DIC for SoC

Monolithic 3DIC integration may provide a viable alternative to conventional 2D scaling for SoCs if manufacturing problems can be overcome.
May 29, 2014
Near-threshold computing for minimum energy - thumbnail

Near-threshold and subthreshold logic

By taking the circuit supply voltage close to that of the threshold voltage or even below, it is possible to optimize low-power VLSI design. But there are pitfalls.
May 26, 2014

Design for security

Design for security is an emerging topic in hardware engineering demanding a more holistic approach that traditional cryptographic implementation.
May 24, 2014
Dopant-level trojan standard cell developed by Georg Becker and coworkers

Hardware trojan attacks and countermeasures

IC designers are becoming increasingly worried about the possibility of third parties inserting malicious 'trojan' circuitry into their ICs.
May 19, 2014

On-chip clock strategies and GALS

The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
May 19, 2014

10nm processes

The 10nm generation is the follow-on process to the 14nm/16nm node and will provide a choice of either finFET or planar FD-SOI architectures. But the likely absence of EUV will increase costs.

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