
Speeding AMS verification by easing simulation debug and analysis
How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
The paper presents a fully parallel transistor-level full-chip circuit simulation tool with SPICE accuracy for general circuit designs. The proposed overlapping domain decomposition approach partitions the circuit into a linear subdomain and multiple nonlinear subdomains based on circuit nonlinearity and connectivity. A parallel iterative matrix solver is used to solve the linear domain while nonlinear […]