BCI-ROM: a game-changer for electro-thermal design
The Boundary Condition Independent Reduced Order Model (BCI-ROM) provides vital help in addressing growing electro-thermal challenges in SPICE simulation.
SPICE
Speeding AMS verification by easing simulation debug and analysis
How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
FastSPICE simulators hit their expiration date
Although FastSPICE simulators are in almost every design flow, requirements are moving beyond the capabilities they can provide. Parallel processing provides a solution.
Mixed-signal verification of advanced SoCs using VCS AMS
How ST Microelectronics uses Synopsys' VCS AMS, combining VCS functional verification and CustomSim, to verify one of its mixed-signal designs
One BSIM to rule them all
A change in the way the core compact models are developed has accelerated their development and, for the first time, allowed the models to be used not just for circuit simulation but to help guide process evolution as chipmakers play not only with materials but the shape of finFETs.
Part 2 – Parallel transistor-level full-chip circuit simulation
The paper presents a fully parallel transistor-level full-chip circuit simulation tool with SPICE accuracy for general circuit designs. The proposed overlapping domain decomposition approach partitions the circuit into a linear subdomain and multiple nonlinear subdomains based on circuit nonlinearity and connectivity. A parallel iterative matrix solver is used to solve the linear domain while nonlinear […]
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