DFM

July 5, 2012

Improving ASIC prototyping on multiple FPGAs through better partitioning

Using a new design-partitioning tool and stacked-silicon interconnect FPGA to develop an ASIC prototyping platform that can be reprogrammed several times a day.
June 1, 2012
Michael Buehler-Garcia

DAC 2012: 20(nm) questions

There's still debate over certain aspects of the 20nm node, but the main challenges are already being addressed. Expect to see foundries and vendors mark their turf at DAC.
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May 22, 2012
Jeff Wilson

Making dummy fill smarter

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
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May 22, 2012

Effective finger-pointing: the art of modern yield analysis

Correlating production test failure diagnosis with DFM analysis can help identify and understand systematic yield issues, and to find out whether they are linked to DFM violations.
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May 15, 2012

Decoupled constraint modelling – a design methodology for hard real-time systems on chip

Using UML to define a software-defined modem SoC in terms of decoupled constraints - the order of activities, the timing they have to meet, and the available resources
March 28, 2012

FinFETs

It may be necessary to move to three-dimensional 'FinFET' transistors for future process nodes, but what impact will this have on circuit design?
March 28, 2012

FD-SOI

Fully depleted silicon on insulator (FD-SOI) transistor architectures may offer speed and power advantages, at the cost of a shift to non-standard substrates.
January 16, 2012

Double patterning for sub-28nm ICs

Double patterning provides an alternative to using EUV lithography – making it possible to implement ICs on sub-28nm processes.
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October 19, 2011

Plan for 450mm or pay the price

The launch of a broad-based IDM/foundry consortium that is to prepare for the shift to 450mm wafers already offers some hints as to the future shape of chip manufacturing and the planning demands it will impose on all design managers in the near future. The game is shifting from pay-for-capacity to outright pay-to-play for those [...]
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August 25, 2011

Selective CVD growth of germanium-tin: a new approach for implementing stress in germanium-based MOSFETs

Belgian research institute Imec describes, for the first time, the selective chemical vapor deposition (CVD) of germanium-tin (GeSn) in a production-like environment using commercially available Ge and Sn precursors. The resulting GeSn layers with 8% Sn are defect free, fully strained and thermally stable for temperatures up to 500°C. The technique is used to implement [...]
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